1. Field of the Invention
The present invention generally relates to etching ferroelectric materials and, more particularly, to the formation of protective sidewalls of ferroelectric layers during memory device fabrication.
2. Description of the Related Art
Lead zirconate titanate (PZT), a ferroelectric oxide material, is often used for memory cell applications to create ferroelectric random access memory (FeRAM) devices. Various methods for forming the FeRAM devices and processing PZT have been discussed in the art. One method of forming a FeRAM device is to use two separate masks with two separate etching steps. The first mask and etch step forms the top electrode and the second mask and second etch step etches through the PZT and forms the bottom electrode. This process is not desirable because it is time consuming in that it requires the formation and subsequent stripping of two different masks and two corresponding etch steps to be conducted with formation of the masks. Additionally, since the top and bottom electrodes are typically formed from two different steps, they are usually two different sizes. Such a condition makes it difficult to scale down overall device size, and thereby increase yield on a substrate.
The two mask approach was substituted by a one mask approach in an effort to prevent the top and bottom electrode from having two different sizes. However, when etching various layers (and thereby creating a high sidewall to the devices that are formed) residues collect on the sidewalls. These residues are byproducts of the etching process and typically contain metallic components having low volatility. The metallic residue easily redeposits on the sidewalls of the device and creates a short circuit between top and bottom electrodes of the device which is an undesirable result of one mask etching. It was subsequently considered to create tapered sidewalls in the devices. Creating a tapered sidewall was beneficial in that it enhanced the complete etching and exhausting of byproducts and reducing residues; however, creating a device with a tapered profile changes the overall surface area of the device. Specifically, varying the surface area of the device changes the overall critical dimensions of the device to a value that is typically unacceptably large for the application desired.
Therefore, a need exists for a method of etching ferroelectric layers with reduced by-product formation and increased device reliability and electrical characteristics and desired device size.